This invention relates generally to fabrication of a microelectronic circuits on a silicon substrate to produce an integrated circuit and specifically to a system for efficient design of an integrated circuit by interconnection of predefined microcircuit cores.
The size and complexity of microelectronic circuits fabricated on silicon substrates to make an integrated circuit (IC) are constantly growing. Today's ICs, especially the complex "system on a chip" circuits, include hundreds of thousands of gates and a corresponding larger number of interconnections among the gates. The costs of producing such large scale integrated circuits depends on the resources required for each step in the design phase.
The first step in the design phase is the conceptualization step where a human designer decides broad functionality of the IC chip should have. After the functionality has been determined the designer will produce a high-level circuit description such as a block diagram. Next a more detailed circuit description such as a schematic diagram will be created that specifies the design to the gate level, at least for some of the functionality.
Typically, these circuit descriptions break the design up into functional blocks and show interconnections between the functional blocks. Once the design has been sufficiently described by the circuit descriptions the designer, or design team, will go ahead and prototype the design, if the design is small enough, or may simulate the design on a computer system if the design is large and complex. For large systems a combination of prototyping and simulating is usually employed.
At some point in the design process the designer team decides on an implementation technology for the circuit. This technology can include discrete circuit design, programmed logic array, gate array, custom or semi-custom design, etc. When the circuit is very large a common implementation is to use a the semi-custom approach where the circuit is built up of existing "cells" or "cores" from an existing library of predefined cores. Using the core approach, functional blocks in the circuit description are easily implemented in the design with the existing micro circuits in a predefined core that performs the desired function. Two or more predefined cores are interconnected by metal conductors fabricated on the substrate in any of a variety of process methods as is commonly known in the art. Since all of the functionality of the new design will typically not be achieved with existing cores, additional microcircuitry to perform the missing functionality is designed and fabricated on the chip. This additional microcircuitry is referred to as "custom" or "customer" logic.
An example of a semi-custom implementation is a microprocessor based application that uses cores common to computer systems such as a central processing unit (CPU), memory, input/output (I/O) unit, and customer logic. It will be readily apparent that designs for common cores such as a processor, memory, I/O unit, etc. can be used over and over again in many different chip designs. In each of these different chip designs, while the cores may be the same, the customer logic and interconnections between the cores will vary.
Using standard, or common, cores accelerates the design process for an integrated circuit because the cores, which may consist of many tens of thousands of gates, are predefined and reusable in a variety of designs. However, traditional approaches to using common cores suffer from problems in interconnecting the cores where the system design is complex and uses several cores and custom circuitry. Because the surface area, or process area, on the silicon substrate is limited, the large number of interconnections between cores makes it difficult to adequately route the interconnecting signals. Further, timing design errors are prevalent as clock speeds increase, conductor paths lengthen and fan out and the number of distribution points for a signal increases.
A source of timing design errors occurs where signal skew causes an unanticipated logic condition that must be taken care of by redesigning, rerouting, or making another modification to the design. A major source of timing design errors is in the routing of signals between core cells in the semi-custom IC design. At current system clock rates, even the distribution of a clock signal to different cores may cause problems since the clock will experience different delays depending on the length of the routing path. Current design methods attempt to alleviate some of the burden to human designers in detecting and preventing timing design errors by using computers to simulate the performance of a circuit before the circuit is formed in silicon. However, 30-40% of the design cycle is still spent on timing redesign to correct timing design errors.
Part of the reason timing design errors are so prevalent in today's ICs design cycles is that as IC become denser and clock speeds become greater, the widths of the conductors on ICs are becoming more numerous, closer spaced, greater in length and smaller in width. This causes increased timing errors due to propagation delays and inductive and capacitive effects. Methods to provide larger conductive paths within an IC, such as a "solder bump" metallization and "flip chip" packaging and assembly (also referred to as the "controlled collapse chip connection," or "C4"), only address the problem of providing paths from pads on the substrate to external pins on the IC package.
Timing design errors are magnified in today's approach to using common cores in semi-custom designs because the implementation into silicon is "iterative". That is, the design is implemented in silicon in several steps so that the design team doesn't obtain a complete system in silicon until near the end of the design cycle. This means that different timing design errors manifest at different times in the design cycle. It also means that some timing design errors that are present in the middle of the design cycle are unrelated to the actual design and are not accurate representations of timing design errors that would or would not occur when the entire design is in silicon.
Accordingly, it is desired to improve the design cycle time to implement a design for an electronic system in silicon.